Common Weakness Enumeration

1173

Improper Use of Validation Framework

1174

ASP.NET Misconfiguration: Improper Model Validation

1176

Inefficient CPU Computation

1177

Use of Prohibited Code

1188

Initialization of a Resource with an Insecure Default

1189

Improper Isolation of Shared Resources on System-on-a-Chip (SoC)

1190

DMA Device Enabled Too Early in Boot Phase

1191

On-Chip Debug and Test Interface With Improper Access Control

1192

Improper Identifier for IP Block used in System-On-Chip (SOC)

1193

Power-On of Untrusted Execution Core Before Enabling Fabric Access Control

1204

Generation of Weak Initialization Vector (IV)

1209

Failure to Disable Reserved Bits

1220

Insufficient Granularity of Access Control

1221

Incorrect Register Defaults or Module Parameters

1222

Insufficient Granularity of Address Regions Protected by Register Locks

1223

Race Condition for Write-Once Attributes

1224

Improper Restriction of Write-Once Bit Fields

1229

Creation of Emergent Resource

1230

Exposure of Sensitive Information Through Metadata

1231

Improper Prevention of Lock Bit Modification

1232

Improper Lock Behavior After Power State Transition

1233

Security-Sensitive Hardware Controls with Missing Lock Bit Protection

1234

Hardware Internal or Debug Modes Allow Override of Locks

1235

Incorrect Use of Autoboxing and Unboxing for Performance Critical Operations

1236

Improper Neutralization of Formula Elements in a CSV File

1239

Improper Zeroization of Hardware Register

1240

Use of a Cryptographic Primitive with a Risky Implementation

1241

Use of Predictable Algorithm in Random Number Generator

1242

Inclusion of Undocumented Features or Chicken Bits

1243

Sensitive Non-Volatile Information Not Protected During Debug

1244

Internal Asset Exposed to Unsafe Debug Access Level or State

1245

Improper Finite State Machines (FSMs) in Hardware Logic

1246

Improper Write Handling in Limited-write Non-Volatile Memories

1247

Improper Protection Against Voltage and Clock Glitches

1248

Semiconductor Defects in Hardware Logic with Security-Sensitive Implications

1249

Application-Level Admin Tool with Inconsistent View of Underlying Operating System

1250

Improper Preservation of Consistency Between Independent Representations of Shared State

1251

Mirrored Regions with Different Values

1252

CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations

1253

Incorrect Selection of Fuse Values

1254

Incorrect Comparison Logic Granularity

1255

Comparison Logic is Vulnerable to Power Side-Channel Attacks

1256

Improper Restriction of Software Interfaces to Hardware Features

1257

Improper Access Control Applied to Mirrored or Aliased Memory Regions

1258

Exposure of Sensitive System Information Due to Uncleared Debug Information

1259

Improper Restriction of Security Token Assignment

1260

Improper Handling of Overlap Between Protected Memory Ranges

1261

Improper Handling of Single Event Upsets

1262

Improper Access Control for Register Interface

1263

Improper Physical Access Control